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? semiconductor components industries, llc, 2009 september, 2009 ? rev. 8 1 publication order number: mc14490/d mc14490 hex contact bounce eliminator the mc14490 is constructed with complementary mos enhancement mode devices, and is used for the elimination of extraneous level changes that result when interfacing with mechanical contacts. the digital contact bounce eliminator circuit takes an input signal from a bouncing contact and generates a clean digital signal four clock periods after the input has stabilized. the bounce eliminator circuit will remove bounce on both the ?make? and the ?break? of a contact closure. the clock for operation of the mc14490 is derived from an internal r ? c oscillator which requires only an external capacitor to adjust for the desired operating frequency (bounce delay). the clock may also be driven from an external clock source or the oscillator of another mc14490 (see figure 5). note: immediately after powerup, the outputs of the mc14490 are in indeterminate states. features ? diode protection on all inputs ? six debouncers per package ? internal pullups on all data inputs ? can be used as a digital integrator, system synchronizer, or delay line ? internal oscillator (r ? c), or external clock source ? ttl compatible data inputs/outputs ? single line input, debounces both ?make? and ?break? contacts ? does not require ?form c? (single pole double throw) input signal ? cascadable for longer time delays ? schmitt trigger on clock input (pin 7) ? supply voltage range = 3.0 v to 18 v ? chip complexity: 546 fets or 136.5 equivalent gates ? these are pb ? free devices* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ? 0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ? 0.5 to v dd + 0.5 v input current (dc or transient) per pin i in 10 ma power dissipation, per package (note 1) p d 500 mw ambient temperature range t a ? 55 to +125 c storage temperature range t stg ? 65 to +150 c lead temperature (8 ? second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. soic ? 16 dw suffix case 751g http://onsemi.com 16 1 14490 awlyywwg see detailed ordering and shipping information in the package dimensions section on p age 9 of this data sheet. ordering information a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free package marking diagrams pdip ? 16 p suffix case 648 soeiaj ? 16 f suffix case 966 1 16 mc14490 alywg 16 1 MC14490P awlyywwg 1 1 1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14490 http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d in c out b in v dd osc out f in e out d out c in b out a in v ss osc in f out e in a out block diagram a in 1 osc in 7 osc out 9 b in 14 c in 3 d in 12 e in 5 f in 10 +v dd 1 2 oscillator and two-phase clock generator data shift load 4-bit static shift register 1/2-bit delay 1 2 1 2 15 a out v dd = pin 16 v ss = pin 8 1 2 1 2 1 2 1 2 1 2 2b out 13c out 4d out 11e out 6f out identical to above stage identical to above stage identical to above stage identical to above stage identical to above stage
mc14490 http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) ?????????? ?????????? ?????????? characteristic ???? ???? ???? ??? ??? ??? ????? ????? ? 55 c ????????? ????????? c ????? ????? c ??? ??? ??? ??? ??? ??? ??? ???? ???? ??? ??? (note 2) ???? ???? max ??? ??? ??? ??? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? output voltage ?0? level v in = v dd or 0 ?1? level v in = 0 or v dd ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? 0.05 0.05 0.05 ???? ???? ???? ? ? ? ??? ??? ??? 0 0 0 ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? 0.05 0.05 0.05 ??? ??? ??? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? ???? 4.95 9.95 14.95 ??? ??? ??? ??? ???? ???? ???? ???? ? ? ? ??? ??? ??? ??? 4.95 9.95 14.95 ??? ??? ??? ??? ? ? ? ??? ??? ??? ??? vdc ?????????? ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? 1.5 3.0 4.0 ???? ???? ???? ? ? ? ??? ??? ??? 2.25 4.50 6.75 ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? 1.5 3.0 4.0 ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 3.5 7.0 11 ??? ??? ??? ???? ???? ???? ? ? ? ??? ??? ??? 3.5 7.0 11 ??? ??? ??? ? ? ? ??? ??? ??? vdc ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ? 0.5 ? 0.1 ? 0.2 ? 1.2 ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? ? ? ? ? ??? ??? ??? ??? ??? ? 0.4 ? 0.08 ? 0.16 ? 1.0 ??? ??? ??? ??? ??? ? ? ? ? ??? ??? ??? ??? ??? ??? ??? ??? madc ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ? 0.75 ? 0.16 ? 0.5 ? 1.5 ??? ??? ??? ??? ???? ???? ???? ???? ? ? ? ? ??? ??? ??? ??? ? 0.6 ? 0.12 ? 0.4 ? 1.2 ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? ???? i ol ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? ???? 0.3 0.75 3.5 ??? ??? ??? ??? ???? ???? ???? ???? ? ? ? ??? ??? ??? ??? 0.24 0.6 2.8 ??? ??? ??? ??? ? ? ? ??? ??? ??? ??? ??? ??? ??? madc ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? ???? 2.2 3.3 10 ??? ??? ??? ??? ???? ???? ???? ???? ? ? ? ??? ??? ??? ??? 1.8 2.7 8.1 ??? ??? ??? ??? ? ? ? ?????????? ?????????? input current debounce inputs (v in = v dd ) ???? ???? ??? ??? ??? ??? ? ??? ??? 2.0 ???? ???? ? ??? ??? 0.2 ???? ???? ??? ??? ? ??? ??? 11 ??? ??? adc ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ??? ??? ??? 620 ???? ???? ???? ? ??? ??? ??? 255 ???? ???? ???? 400 ??? ??? ??? ? ??? ??? ??? 250 ??? ??? ??? adc ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? adc ?????????? ?????????? ???? ???? ??? ??? ? ??? ??? ??? ??? ???? ???? ??? ??? 5.0 ???? ???? ??? ??? ? ??? ??? ??? ??? pf ?????????? ?????????? ?????????? a) ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? 150 280 840 ???? ???? ???? ? ? ? ??? ??? ??? 40 90 225 ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? 90 180 550 ??? ??? ??? adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14490 http://onsemi.com 4 switching characteristics (note 3) (c l = 50 pf, t a = 25 c) ?????????????????? ?????????????????? characteristic ????? ????? ??? ??? ??? ??? ???? ???? (note 4) ??? ??? max ??? ??? ?????????????????? ?????????????????? ?????????????????? output rise time all outputs ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 180 90 65 ??? ??? ??? ??? ??? ??? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 100 50 40 ??? ??? ??? ??? ??? ??? ??? ??? ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 60 30 20 ??? ??? ??? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 285 120 95 ??? ??? ??? ??? ??? ??? ??? ??? ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 370 160 120 ??? ??? ??? ?????????????????? ?????????????????? ?????????????????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 2.8 6 9 ??? ??? ??? ??? ??? ??? ?????????????????? ?????????????????? ?????????????????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? ns ?????????????????? ?????????????????? ?????????????????? ????? ????? ????? ??? ??? ??? ???????? ???????? ???????? ??? ??? ??? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? 100 pf* note: these equations are intended to be a design guide. laboratory experimentation may be required. formulas are typically 15% of actual frequencies. ????? ????? ????? ????? ????? ????? ??? ??? ??? ??? ??? ??? ???????? ???????? ???????? ???????? ???????? ???????? f) 4.5 c ext (in f) 6.5 c ext (in f) ??? ??? ??? ??? ??? ??? c. 4. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. *power ? down considerations large values of c ext may cause problems when powering down the mc14490 because of the amount of energy stored in the capacitor. when a system containing this device is powered down, the capacitor may discharge through the input protection diodes at pin 7 or the parasitic diodes at pin 9. current through these internal diodes must be limited to 10 ma, therefore the turn ? off time of the power supply must not be faster than t = (v dd ? v ss ) c ext / (10 ma). for example, if v dd ? v ss = 15 v and c ext = 1 f, the power supply must turn of f no faster than t = (15 v) (1 f) / 10 ma = 1.5 ms. this is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. when a more rapid decrease of the power supply to zero volts occurs, the mc14490 may sustain damage. to avoid this possibility, use external clamping diodes, d1 and d2, connected as shown in figure 2. figure 1. switching waveforms figure 2. discharge protection during power down osc in a out a out osc in a in v dd 0 v v dd 0 v v dd 0 v 50% 90% 50% 10% t r t f t phl 90% 10% 50% 50% t su 50% d1 d2 c ext 9 7 osc in osc out mc14490 t plh v dd v dd
mc14490 http://onsemi.com 5 theory of operation the mc14490 hex contact bounce eliminator is basically a digital integrator. the circuit can integrate both up and down. this enables the circuit to eliminate bounce on both the leading and trailing edges of the signal, shown in the timing diagram of figure 3. each of the six bounce eliminators is composed of a 4 ? 1/2 ? bit register (the integrator) and logic to compare the input with the contents of the shift register, as shown in figure 4. the shift register requires a series of timing pulses in order to shift the input signal into each shift register location. these timing pulses (the clock signal) are represented in the upper waveform of figure 3. each of the six bounce eliminator circuits has an internal resistor as shown in figure 4. a pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such as those coming from relay contacts and push buttons. by switching ground, rather than a power supply lead, system faults (such as shorts to ground on the signal input leads) will not cause excessive currents in the wiring and contacts. signal lead shorts to ground are much more probable than shorts to a power supply lead. when the relay contact is closed, (see figure 4) the low level is inverted, and the shift register is loaded with a high on each positive edge of the clock signal. to understand the operation, we assume all bits of the shift register are loaded with lows and the output is at a high level. at clock edge 1 (figure 3) the input has gone low and a high has been loaded into the first bit or storage location of the shift register. just after the positive edge of clock 1, the input signal has bounced back to a high. this causes the shift register to be reset to lows in all four bits ? thus starting the timing sequence over again. during clock edges 3 to 6 the input signal has stayed low. thus, a high has been shifted into all four shift register bits and, as shown, the output goes low during the positive edge of clock pulse 6. it should be noted that there is a 3 ? 1/2 to 4 ? 1/2 clock period delay between the clean input signal and output signal. in this example there is a delay of 3.8 clock periods from the beginning of the clean input signal. after some time period of n clock periods, the contact is opened and at n + 1 a low is loaded into the first bit. just after n + 1, when the input bounces low, all bits are set to a high. at n +2 nothing happens because the input and output are low and all bits of the shift register are high. at time n +3 and thereafter the input signal is a high, clean signal. at the positive edge of n+ 6 the output goes high as a result of four lows being shifted into the shift register. assuming the input signal is long enough to be clocked through the bounce eliminator, the output signal will be no longer or shorter than the clean input signal plus or minus one clock period. the amount of time distortion between the input and output signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency. since most relay contacts have more bounce when making as compared to breaking, the overall delay, counting bounce period, will be greater on the leading edge of the input signal than on the trailing edge. thus, the output signal will be shorter than the input signal ? if the leading edge bounce is included in the overall timing calculation. the only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state. referring to figure 3, a false state is seen to occur three times at the beginning of the input signal. the input signal goes low three times before it finally settles down to a valid low state. the first three low pulses are referred to as false states. if the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). however, if an external clock is not available the user can place a small capacitor across the oscillator input and output pins in order to start up an internal clock source (as shown in figure 4). the clock signal at the oscillator output pin may then be used to clock other mc14490 bounce eliminator packages. with the use of the mc14490, a large number of signals can be cleaned up, with the requirement of only one small capacitor external to the hex bounce eliminator packages. figure 3. timing diagram osc in or osc out input output contact open contact bouncing contact closed (valid true signal) contact bouncing contact open n + 7 n + 5 n + 3 n + 1 6 5 4 3 2 1
mc14490 http://onsemi.com 6 figure 4. typical ?form a? contact debounce circuit (only one debouncer shown) 1/2 bit delay oscillator and two-phase clock generator c ext osc out osc in form a contact a in 1 9 7 1 2 data shift load 4-bit static shift register 1 2 1 2 15 a out +v dd pullup resistor (internal) operating characteristics the single most important characteristic of the mc14490 is that it works with a single signal lead as an input, making it directly compatible with mechanical contacts (form a and b). the circuit has a built ? in pullup resistor on each input. the worst case value of the pullup resistor (determined from the electrical characteristics table) is used to calculate the contact wetting current. if more contact current is required, an external resistor may be connected between v dd and the input. because of the built ? in pullup resistors, the inputs cannot be driven with a single standard cmos gate when v dd is below 5 v. at this voltage, the input should be driven with paralleled standard gates or by the mc14049 or mc14050 buffers. the clock input circuit (pin 7) has schmitt trigger shaping such that proper clocking will occur even with very slow clock edges, eliminating any need for clock preshaping. in addition, other mc14490 oscillator inputs can be driven from a single oscillator output buffered by an mc14050 (see figure 5). up to six mc14490s may be driven by a single buffer. the mc14490 is ttl compatible on both the inputs and the outputs. when v dd is at 4.5 v, the buffered outputs can sink 1.6 ma at 0.4 v. the inputs can be driven with ttl as a result of the internal input pullup resistors. figure 5. typical single oscillator debounce system from contacts mc14490 to system logic osc in osc out c ext 1/6 mc14050 9 7 osc in 7 9osc out no connection from contacts to system logic mc14490 no connection 9osc out osc in 7 from contacts mc14490 to system logic
mc14490 http://onsemi.com 7 typical applications asymmetrical timing in applications where different leading and trailing edge delays are required (such as a fa st attack/slow release timer.) clocks of different frequencies can be gated into the mc14490 as shown in figure 6. in order to produce a slow attack/fast release circuit leads a and b should be interchanged. the clock out lead can then be used to feed clock signals to the other mc14490 packages where the asymmetrical input/output timing is required. figure 6. fast attack/slow release circuit in out osc out mc14011b osc in ab f c/n external clock n f c mc14490 latched output the contents of the bounce eliminator can be latched by using several extra gates as shown in figure 7. if the latch lead is high the clock will be stopped when the output goes low. this will hold the output low even though the input has returned to the high state. any time the clock is stopped the outputs will be representative of the input signal four clock periods earlier. figure 7. latched output circuit in out osc out mc14011b osc in mc14490 clock latch = 1 unlatch = 0 multiple timing signals as shown in figure 8, the bounce eliminator circuits can be connected in series. in this configuration each output is delayed by four clock periods relative to its respective input. this configuration may be used to generate multiple timing signals such as a delay line, for programming other timing operations. one application of the above is shown in figure 9, where it is required to have a single pulse output for a single operation (make) of the push button or relay contact. this only requires the series connection of two bounce eliminator circuits, one inverter, and one nor gate in order to generate the signal a b as shown in figures 9 and 10. the signal a b is four clock periods in length. if the inverter is switched to the a output, the pulse a b will be generated upon release or break of the contact. with the use of a few additional parts many different pulses and waveshapes may be generated. figure 8. multiple timing circuit connections 10 5 12 3 14 1 79 6 11 4 13 2 15 a out b out c out d out e out f out osc in clock b.e. 6 b.e. 5 b.e. 4 b.e. 3 b.e. 2 b.e. 1 osc out a in b in c in d in e in f in
mc14490 http://onsemi.com 8 figure 9. single pulse output circuit in in a out out b a b a b a active low b active low be 2 be 1 figure 10. multiple output signal timing diagram osc in or osc out input a b c d e f a b ab
mc14490 http://onsemi.com 9 ordering information device package shipping ? mc14490dwg soic ? 16 (pb ? free) 47 units / rail mc14490dwr2g soic ? 16 (pb ? free) 1000 / tape & reel mc14490fg soeiaj ? 16 (pb ? free) 50 units / rail mc14490felg soeiaj ? 16 (pb ? free) 2000 units / tape & reel MC14490Pg pdip ? 16 (pb ? free) 25 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc14490 http://onsemi.com 10 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip ? 16 case 648 ? 08 issue t so ? 16 wb case 751g ? 03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7
mc14490 http://onsemi.com 11 package dimensions soeiaj ? 16 case 966 ? 01 issue a h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc14490/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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